Software-Defined Radio System Architecture

This document presents a systematic treatment of software-defined radio (SDR) architecture, covering the complete signal path from antenna to demodulated data. SDR systems replace fixed-function analog circuits with programmable digital signal processing, enabling a single hardware platform to implement arbitrary radio standards through software configuration. The treatment emphasizes practical design trade-offs, real component parameters, and the signal-theoretic foundations that govern system performance.

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1. Introduction

1.1 From Hardware to Software

Traditional radio receivers implement frequency selection, demodulation, and filtering using analog circuits optimized for specific signal types. A crystal radio selects one station; a superheterodyne receiver is built for one modulation scheme and bandwidth. Software-defined radio moves these functions into the digital domain, performing signal processing on digitized samples rather than continuous-time signals.

The concept was first formalized by Mitola (1991), who proposed the “ideal software radio” — a system where the ADC sits directly at the antenna, digitizing the entire electromagnetic spectrum, with all selectivity and demodulation performed in software. While this ideal remains impractical (the RF spectrum spans DC to 300 GHz, requiring absurdly high sample rates and bit depths), modern SDR systems approximate it within practical bands by placing the ADC as close to the antenna as technology allows.

1.2 The Practical SDR Continuum

Real SDR systems exist on a continuum between fully analog and fully digital:

Level	Description	ADC Position	Example
0	Fully analog	None	Crystal radio
1	Software-controlled	After full demod	Scanner with serial control
2	Software-defined (IF)	After IF stage	WinRadio, IC-7610
3	Software-defined (RF)	After LNA	RTL-SDR, ANAN-G2
4	Ideal software radio	At antenna	Theoretical limit

Table 1 The SDR continuum from analog to ideal.

This document focuses on Level 2–3 architectures, which represent the current state of practical SDR engineering.

1.3 Advantages and Trade-offs

Characteristic	Traditional Radio	Software-Defined Radio
Flexibility	Fixed modulation	Arbitrary waveforms
Reconfigurability	Hardware modification	Software update
Multi-mode operation	Separate receivers	Single platform
Obsolescence	Hardware-limited	Software-upgradeable
Power consumption	Lower (analog)	Higher (digital processing)
Dynamic range	Excellent (analog AGC)	ADC-limited
Latency	Near-zero (analog)	Processing pipeline delay

Table 2 SDR versus traditional radio characteristics.

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2. System Architecture Overview

2.1 Canonical SDR Block Diagram

The SDR signal chain comprises the following functional stages, progressing from the RF domain through analog-to-digital conversion into the digital processing domain:

Figure 1 Canonical SDR receiver signal chain showing the complete path from antenna to decoded output. The dashed vertical line marks the analog-to-digital boundary. Sample rates are annotated at each stage. The LO/Synthesizer controls the analog mixer while the CLK REF (OCXO) provides the ADC sampling clock.

Stage	Component	Domain	Function
1	Antenna	RF	Signal capture (50 Ω reference)
2	Preselector BPF	RF	Band selection, out-of-band rejection
3	LNA	RF	Low-noise amplification (20–30 dB)
4	Mixer + LO	RF	Frequency translation to IF (optional)
5	IF Filter	RF	Channel selectivity (roofing filter)
6	AGC	RF	Automatic gain control
7	Anti-alias Filter	RF	Sample rate-limited bandwidth
8	ADC	RF → Digital	Analog-to-digital conversion
9	DDC (NCO + CIC + FIR)	Digital	Digital down-conversion to baseband
10	Channelizer	Digital	Channel selection and filtering
11	Demodulator	Digital	Symbol recovery
12	FEC Decoder	Digital	Error correction and framing

Table 3 SDR receiver signal chain stages.

The LO/Synthesizer controls the analog mixer (if present), while the NCO (Numerically-Controlled Oscillator) controls digital frequency translation in the DDC. Zero mixer stages corresponds to direct RF sampling; multiple mixer stages enable higher frequency operation with relaxed ADC requirements.

2.2 Architecture Classifications

The placement of the ADC relative to the antenna defines the SDR architecture classification. Each approach represents a different balance between analog complexity and digital processing demands:

Figure 2 Three principal SDR architectures showing ADC placement (gray blocks). (a) Direct RF sampling eliminates the mixer entirely. (b) Superheterodyne conversion relaxes ADC bandwidth requirements at the cost of analog complexity. (c) Zero-IF produces baseband I/Q directly but introduces DC offset and LO leakage artifacts.

Architecture	ADC Position	Typical Range	ADC Speed Required	Analog Complexity
Direct RF sampling	After LNA	DC–100 MHz	Very high (>250 MSPS)	Minimal
Single conversion	After one mixer	100 MHz–6 GHz	Medium (50–250 MSPS)	Moderate
Dual conversion	After two mixers	1–40 GHz	Low (10–50 MSPS)	High
Direct conversion (Zero-IF)	At baseband (I/Q)	All	Low–Medium	Moderate (I/Q paths)

Table 4 SDR architecture classifications by ADC position.

2.3 Architecture Selection Criteria

The choice between architectures depends on operating frequency, instantaneous bandwidth, dynamic range requirements, and system complexity budget:

• HF bands (1.8–30 MHz): Direct RF sampling is preferred. Modern 14–16 bit ADCs at 125+ MSPS can digitize the entire HF spectrum in a single Nyquist zone. This is the architecture used in the ANAN-G2 and similar HPSDR platforms.
• VHF/UHF (30 MHz–3 GHz): Single conversion or direct conversion. The choice depends on whether wideband coverage (superhet) or integration density (zero-IF) is prioritized.
• Microwave (>3 GHz): Dual conversion is typical, though direct sampling ADCs are pushing into the 5–10 GHz range with RF-class ADCs (e.g., TI ADC12DJ5200RF at 10.4 GSPS).

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3. RF Front-End Design

The RF front-end conditions the analog signal for digitization. Its performance establishes the system noise floor, dynamic range, and spurious-free operating region. Every component in the analog chain either adds noise or adds distortion — the art of front-end design is managing both simultaneously.

Figure 3 Complete RF front-end signal chain with component specifications. The lower portion shows the signal level budget for a typical weak-signal case (-80 dBm input), tracing power levels through each stage to the ADC input.

3.1 Low-Noise Amplifier

The LNA establishes system noise performance. The Friis equation for cascaded noise figure:

F_total = F₁ + (F₂ - 1)/G₁ + (F₃ - 1)/(G₁G₂) + … — Eq. (1)

Where F = noise factor (linear, not dB), G = gain (linear). The first-stage noise factor dominates total system noise figure because subsequent stage contributions are divided by the cumulative gain preceding them. This is why the LNA is the most critical component in the receiver chain.

For practical design, converting to dB:

NF_total ≈ NF_LNA + (NF₂ - 1 dB) / G_LNA — Eq. (2) (approximate, for high G_LNA)

LNA design parameters vary by frequency range due to device physics and atmospheric noise:

Parameter	HF (1.8–30 MHz)	VHF/UHF (30–1000 MHz)	Microwave (1–10 GHz)
Noise Figure	1–3 dB	0.5–1.5 dB	0.8–2.0 dB
Gain	20–30 dB	15–25 dB	15–20 dB
OIP3	+20 to +30 dBm	+10 to +25 dBm	+5 to +15 dBm
P1dB	+10 to +15 dBm	0 to +10 dBm	-5 to +5 dBm
Technology	JFET, BJT	GaAs pHEMT	GaAs/GaN MMIC

Table 5 LNA specifications by frequency range.

Design note (HF): At HF frequencies, external noise (atmospheric, man-made) often exceeds thermal noise by 20–40 dB. This means LNA noise figure is less critical than linearity (IP3). A 3 dB NF LNA with +30 dBm OIP3 is preferable to a 0.5 dB NF LNA with +15 dBm OIP3 in an HF application.

3.2 Dynamic Range Analysis

The two critical dynamic range measures for an SDR front-end are:

Spurious-Free Dynamic Range (SFDR) — the ratio between a maximum on-channel signal and the largest spurious product from two-tone intermodulation:

SFDR = (2/3)(IIP3 - NF_floor) — Eq. (3)

Where NF_floor = -174 dBm/Hz + NF + 10 log₁₀(BW).

Blocking Dynamic Range (BDR) — the ratio between a maximum off-channel signal (that compresses the receiver by 1 dB) and the minimum detectable signal:

BDR = P_1dB - MDS — Eq. (4)

MDS = -174 + NF + 10 log₁₀(BW) + SNR_required — Eq. (5)

Worked example for an HF SDR receiver front-end (BW = 2.4 kHz SSB):

NF = 10 dB, IIP3 = +10 dBm, P_1dB = 0 dBm

Noise Floor = -174 + 10 + 33.8 = -130.2 dBm

MDS = -130.2 + 10 (SNR for copy) = -120.2 dBm

SFDR = (2/3)(10 - (-130.2)) = 93.5 dB

BDR = 0 - (-120.2) = 120.2 dB

3.3 Mixing and Frequency Translation

Heterodyne conversion translates the RF signal to a lower intermediate frequency (IF) where filtering is easier and ADC requirements are relaxed:

f_IF = |f_RF - f_LO| — Eq. (6)

The mixer is inherently a nonlinear device. An ideal mixer produces only sum and difference frequencies, but real mixers produce a family of intermodulation products at f = m · f_RF ± n · f_LO for all integer m, n. The most troublesome is the image response:

Architecture	Image Frequency	Rejection Method	Typical Rejection
High-side injection	fRF + 2fIF	Preselector filter	>60 dB
Low-side injection	fRF - 2fIF	Preselector filter	>60 dB
Hartley image reject	N/A (cancelled)	I/Q phase cancellation	30–45 dB
Weaver image reject	N/A (cancelled)	Dual conversion cancel	40–55 dB

Table 6 Image rejection by mixer architecture.

Mixer performance specifications:

Parameter	Passive (diode ring)	Active (Gilbert cell)
Conversion loss/gain	-6 to -8 dB (loss)	+5 to +15 dB (gain)
IIP3	+15 to +30 dBm	+5 to +15 dBm
Noise figure	6–8 dB	8–15 dB
LO drive	+7 to +17 dBm	-5 to +5 dBm
Port isolation	30–40 dB	20–35 dB

Table 7 Mixer type comparison.

3.4 Automatic Gain Control

The AGC subsystem adjusts receiver gain to keep the ADC within its optimal operating range. The AGC must handle signals from the noise floor (approximately -130 dBm in 500 Hz BW) to strong local signals (+10 dBm at the antenna). This represents a ~140 dB dynamic range that must be compressed into the ADC’s ~80 dB range (14-bit).

AGC design parameters:

Parameter	Typical Value	Design Rationale
Attack time	1–10 ms	Fast enough to prevent ADC clipping
Decay time	100–1000 ms	Slow enough to avoid pumping on speech
Gain range	60–100 dB	Cover expected signal range
Gain steps	0.5–1 dB	Fine enough for smooth AGC action
Threshold	ADC -6 dBFS	Leave headroom for peaks

Table 8 AGC design parameters.

3.5 Anti-Aliasing Filter

The anti-aliasing filter (AAF) must attenuate all signals above f_s/2 to below the ADC noise floor. For a 14-bit ADC (86 dB SNR), the AAF must provide at least 90 dB rejection at the Nyquist frequency.

For direct RF sampling of the HF band (0–62.5 MHz with f_s = 125 MSPS), a 9th-order elliptic lowpass filter is typical:

Parameter	Specification
Passband	DC–30 MHz
Passband ripple	<0.5 dB
-3 dB point	35 MHz
Stop band start	62.5 MHz
Stop band rejection	>90 dB
Insertion loss	<1 dB
Group delay variation	<50 ns across passband

Table 9 Anti-aliasing filter specification for HF direct sampling.

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4. Analog-to-Digital Conversion

The ADC is the pivotal component in any SDR system — it determines the instantaneous bandwidth, dynamic range, and ultimate sensitivity of the receiver. All signal processing after the ADC operates on quantized, sampled data, so any information lost at this stage cannot be recovered.

4.1 Fundamental Sampling Constraints

The Nyquist-Shannon sampling theorem requires:

f_s ≥ 2 · B — Eq. (7)

Where f_s = sample rate, B = signal bandwidth. This is the minimum for perfect reconstruction; in practice, oversampling ratios of 2.5–4× are used to ease anti-aliasing filter requirements and improve SNR through processing gain.

4.2 ADC Performance Parameters

Parameter	Definition	Typical Range	Impact on SDR
Sample rate	Maximum conversion frequency	10–500 MSPS	Sets instantaneous bandwidth
Resolution	Number of output bits	8–16 bits	Sets theoretical dynamic range
ENOB	Effective bits after noise/distortion	6–14 bits	Actual dynamic range
SNR	Signal-to-quantization-noise ratio	50–96 dB	Weak signal sensitivity
SFDR	Spurious-free dynamic range	60–100 dB	Strong signal handling
Aperture jitter	Sample timing uncertainty	50–500 fs RMS	Limits usable bandwidth
Full-scale voltage	Maximum input swing	1–2 Vpp	Sets input power reference

Table 10 ADC performance parameters.

4.3 Quantization Noise

For an ideal N-bit ADC with a full-scale sinusoidal input, the signal-to-quantization-noise ratio is:

SNR_q = 6.02N + 1.76 dB — Eq. (8)

This assumes quantization noise is uniformly distributed and white — an approximation that holds for signals much larger than 1 LSB. In practice, the Effective Number of Bits (ENOB) accounts for all noise and distortion:

ENOB = (SINAD - 1.76) / 6.02 — Eq. (9)

Where SINAD = Signal-to-Noise-and-Distortion ratio.

Bits	Theoretical SNR	Typical ENOB	Typical SINAD	Dynamic Range
8	49.9 dB	7.0	43.9 dB	48 dB
12	74.0 dB	10.5	65.0 dB	72 dB
14	86.0 dB	12.0	74.0 dB	84 dB
16	98.1 dB	13.5	83.0 dB	96 dB

Table 11 ADC resolution and effective performance.

4.4 Nyquist Zones and Bandpass Sampling

When the signal bandwidth B is narrow relative to carrier frequency f_c, bandpass sampling (undersampling) enables digitization of signals above f_s/2 by intentionally aliasing them into the first Nyquist zone:

Figure 4 (a) Nyquist zones for f_s = 125 MSPS. A signal at 150 MHz (Zone 3) aliases to 25 MHz in Zone 1. (b) Valid sample rate regions for a 10 MHz bandwidth signal centered at 150 MHz. The constraint is 2f_H/n ≤ f_s ≤ 2f_L/(n-1).

The Nyquist zones are:

Zone n	Frequency Range	Alias Behavior
1 (baseband)	0 to fs/2	Direct (no aliasing)
2	fs/2 to fs	Spectrum inversion
3	fs to 3fs/2	Direct (same as zone 1)
4	3fs/2 to 2fs	Spectrum inversion

Table 12 Nyquist zone properties. Even zones produce spectral inversion.

Valid bandpass sampling rates must satisfy:

2f_H/n ≤ f_s ≤ 2f_L/(n-1) — Eq. (10)

Where f_L, f_H are signal band edges and n is the target Nyquist zone number.

4.5 Aperture Jitter Analysis

Clock jitter is the fundamental limit on ADC performance at high input frequencies. The SNR degradation from aperture jitter is:

SNR_jitter = -20 log₁₀(2π · f_in · t_j) — Eq. (11)

Where f_in = input signal frequency and t_j = RMS aperture jitter. This is independent of ADC resolution — jitter limits performance even for an infinite-bit ADC.

Input Frequency	100 fs jitter	200 fs jitter	500 fs jitter
10 MHz	90.1 dB	84.0 dB	76.0 dB
30 MHz	80.5 dB	74.5 dB	66.5 dB
70 MHz	73.1 dB	67.1 dB	59.1 dB
150 MHz	66.5 dB	60.5 dB	52.5 dB
500 MHz	56.0 dB	50.0 dB	42.0 dB

Table 13 SNR limit from aperture jitter (dB). Values below the ADC’s native SNR become the system bottleneck.

This is why high-quality clock sources (OCXO or low-jitter crystal oscillators) are critical for SDR performance, especially when using bandpass sampling of high-frequency signals.

4.6 Processing Gain from Oversampling

Oversampling provides processing gain that effectively increases ADC resolution. When sampling at M times the Nyquist rate, then decimating by M:

SNR_improvement = 10 log₁₀(M) — Eq. (12)

Every factor of 4 in oversampling adds approximately 1 effective bit (6 dB). For an HF SDR sampling at 125 MSPS with a 3 kHz SSB channel:

M = 125,000,000 / (2 × 3,000) = 20,833

Processing gain = 10 log₁₀(20,833) = 43.2 dB ≈ 7.2 additional bits

This is why a 14-bit ADC at 125 MSPS can achieve an effective dynamic range exceeding 120 dB in a narrow channel — the oversampling ratio is enormous.

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5. Digital Down-Conversion

The DDC translates a digitized signal from its sampled IF (or RF) frequency down to complex baseband (I/Q), while simultaneously reducing the sample rate through decimation. This is the digital equivalent of the analog mixer + filter chain, but with perfect repeatability and zero drift.

5.1 DDC Architecture

Figure 5 Complete DDC architecture showing dual I/Q paths. The NCO generates quadrature (cos/sin) sequences that mix the digitized signal to baseband. The CIC filter performs coarse decimation (128×), followed by compensation FIR, half-band filter (2× decimation), and final channel-selection FIR (2×). Total decimation = 512, reducing 125 MSPS to 244.1 kSPS. Bit widths grow through the CIC due to accumulator bit growth and are truncated after compensation.

5.2 Numerically-Controlled Oscillator

The NCO generates digital sine/cosine sequences for frequency translation. It replaces the analog LO/VCO with a purely digital frequency synthesizer that has zero phase noise, infinite tuning resolution, and instantaneous frequency switching.

The NCO consists of a phase accumulator and a sin/cos lookup table (or CORDIC processor):

φ[n] = (φ[n-1] + Δφ) mod 2^W — Eq. (13)

I_LO[n] = cos(2πφ[n] / 2^W) — Eq. (14a)

Q_LO[n] = sin(2πφ[n] / 2^W) — Eq. (14b)

Where W = phase accumulator width (bits) and Δφ = frequency tuning word.

The frequency tuning word relates to the desired output frequency:

Δφ = round(f_NCO · 2^W / f_s) — Eq. (15)

Parameter	Typical Value	Design Impact
Phase accumulator width	32 bits	Frequency resolution: fs/232 = 0.029 Hz at 125 MSPS
LUT size	212 to 214 entries	SFDR: >100 dBc with 14-bit LUT
Output width	16–18 bits	Sufficient for 14-bit ADC data
Spurious performance	-100 to -120 dBc	Dithering and Taylor correction improve this
Switching time	1 sample period (8 ns)	Instantaneous retuning

Table 14 NCO performance parameters.

CORDIC vs. LUT: FPGA implementations may use CORDIC (COordinate Rotation DIgital Computer) instead of a lookup table. CORDIC computes sin/cos iteratively using only shifts and adds (no multipliers), trading area for latency. LUT approaches are faster but consume block RAM. Modern FPGAs often have enough block RAM that a quarter-wave LUT with symmetry exploitation is preferred.

5.3 Digital Mixing

Complex mixing translates the signal to baseband. The input real-valued sample x[n] is multiplied by both quadrature components:

I_BB[n] = x[n] · cos(2πf_NCOn/f_s) — Eq. (16a)

Q_BB[n] = -x[n] · sin(2πf_NCOn/f_s) — Eq. (16b)

The result is a complex baseband signal z[n] = I[n] + jQ[n]. This contains both the desired signal (now centered at DC) and a double-frequency component at 2f_NCO that must be removed by subsequent filtering. The complex representation preserves both amplitude and phase information, enabling coherent demodulation of any modulation type.

5.4 CIC Decimation Filter

The Cascaded Integrator-Comb (CIC) filter is the workhorse of high-ratio decimation in SDR systems because it requires no multiplications — only additions and subtractions — making it extremely resource-efficient on FPGAs.

Figure 6 Internal structure of a 3rd-order CIC decimation filter. The integrator section runs at the input sample rate f_s, accumulating sums via recursive feedback. The rate change element discards R-1 of every R samples. The comb section runs at the reduced rate f_s/R, computing running differences. The bottom shows the sinc-like magnitude response with nulls at multiples of f_s/R.

The CIC transfer function is:

H(z) = [(1 - z^-RM) / (1 - z^-1)]^N — Eq. (17)

Where R = decimation rate, M = differential delay (usually 1), N = number of stages.

The magnitude response is a sinc^N function:

|H(f)| = |sin(πMRf/f_s) / sin(πf/f_s)|^N — Eq. (18)

CIC Design Parameter	Typical Value	Consideration
Order (N)	3–5	Higher order = more out-of-band rejection, more passband droop
Decimation (R)	8–256	Higher R requires more integrator bits
Differential delay (M)	1	M=2 improves alias rejection but doubles bit growth
Integrator bit width	N·log2(RM) + Bin	Must accommodate full bit growth
Passband droop at 0.4·fout/2	0.3–1.5 dB	Compensated by subsequent FIR

Table 15 CIC filter design parameters.

Bit growth: The CIC integrator accumulators grow by N·log₂(RM) bits. For N=5, R=128, M=1: growth = 5 × 7 = 35 bits. Starting from 14-bit ADC data, the integrator must be at least 49 bits wide. The comb output is then truncated back to a manageable width (typically 24 bits) before the compensation FIR.

5.5 Decimation Filter Chain

After the CIC, a chain of progressively finer filters shapes the final channel response:

Stage	Filter Type	Decimation	Purpose	Coefficients
1	CIC	64–256×	Coarse decimation, no multipliers	0 (recursive)
2	Compensation FIR	1×	Correct CIC passband droop (sinc-N)	15–31 taps
3	Half-band FIR	2×	Transition band shaping	~50% are zero
4	Channel FIR	2–4×	Final channel selectivity	32–128 taps

Table 16 Typical DDC decimation filter chain.

Half-band filters are particularly efficient because approximately half their coefficients are exactly zero (by the half-band design constraint), halving the multiply count. The center coefficient is exactly 0.5, further saving one multiplication.

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6. Baseband Signal Processing

6.1 I/Q Signal Processing

All modern SDR systems represent signals as complex baseband (I/Q) pairs. This representation is fundamental to coherent processing because it preserves the full analytic signal — both amplitude and instantaneous phase.

Figure 7 (a) Quadrature mixing concept: the input is multiplied by cos and -sin from the NCO to produce I and Q components. The complex baseband signal z[n] = I[n] + jQ[n] is a single-sideband analytic representation. The constellation diagram shows how I and Q encode amplitude and phase. (b) I/Q imbalance correction using an adaptive matrix. (c) DC offset removal using an IIR averaging loop.

Key properties of complex baseband:

• Instantaneous amplitude: A[n] = √(I[n]² + Q[n]²)
• Instantaneous phase: θ[n] = arctan(Q[n] / I[n])
• Instantaneous frequency: f[n] = (1/2π) · dθ/dt ≈ (θ[n] - θ[n-1]) · f_s / (2π)
• Positive/negative frequency discrimination: Complex signals distinguish +f from -f, enabling SSB reception and image rejection in the digital domain.

6.2 Channelization

For multi-channel reception (e.g., monitoring multiple frequencies simultaneously), polyphase filter banks efficiently extract multiple channels from a wideband digitized spectrum:

Method	Channels	Computational Efficiency	Channel Flexibility
Per-channel DDC	1–8	Low (N · single DDC)	Full (arbitrary tuning)
Polyphase filter bank	16–1024	High (shared computation)	Low (uniform spacing)
DFT filter bank (PFB-FFT)	64–4096	Very high (FFT-based)	Low (uniform spacing)
Non-uniform filter bank	Variable	Medium	High (arbitrary bandwidths)

Table 17 Channelization approaches.

The polyphase filter bank + FFT (PFB-FFT) channelizer is the most computationally efficient approach for large numbers of uniformly-spaced channels. It computes all channels simultaneously using a polyphase decomposition of a prototype lowpass filter followed by an FFT. For K channels, the computational cost is O(K log₂ K) per output sample, compared to O(K²) for individual DDCs.

6.3 Demodulation Algorithms

With the signal at complex baseband, demodulation extracts the information-bearing content:

Modulation	Algorithm	Complexity (MFLOPS/ksps)	Key Operations
AM	Envelope detection: √(I2+Q2)	2	Magnitude computation
FM	Arctan differentiation: dθ/dt	10	Arctangent, subtract
SSB	Weaver or phasing method	15	Hilbert FIR, add/subtract
CW	Narrow BPF + envelope	5	FIR filter, magnitude
BPSK/QPSK	Costas loop + matched filter	30	PLL, correlator
16-QAM	Carrier recovery + equalizer	50	PLL, LMS adaptive filter
OFDM	FFT + channel estimation	100	FFT, matrix inversion

Table 18 Demodulation computational requirements.

6.4 Synchronization

Reliable demodulation requires four synchronization functions, each operating at a different time scale:

Function	Algorithm	Convergence	Accuracy Required
Coarse frequency	FFT peak detection	Fast (1 block)	±1 sub-carrier
Fine frequency	PLL (2nd-order type II)	Moderate (10–100 symbols)	<1% of symbol rate
Symbol timing	Gardner TED, Mueller-Müller	Moderate (50–200 symbols)	<5% of symbol period
Frame sync	Correlation with known preamble	Fast (1 frame)	Exact alignment

Table 19 Synchronization functions and algorithms.

The Phase-Locked Loop (PLL) is the fundamental building block for carrier and timing recovery. A digital PLL consists of:

1. Phase detector — measures phase error between input and local reference (multiply + filter)
2. Loop filter — a proportional-integral (PI) controller that determines tracking bandwidth and damping
3. NCO — generates the local frequency/phase reference from the filtered error

The loop bandwidth B_L controls the trade-off between noise rejection (narrow B_L) and acquisition speed (wide B_L). Typical values range from 0.01 · R_sym to 0.05 · R_sym.

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7. Implementation Platforms

7.1 FPGA-CPU Partitioning

Modern SDR systems use a heterogeneous architecture: an FPGA handles the high-sample-rate, deterministic processing, while a CPU handles complex, variable-rate algorithms. The boundary between them is set by sample rate and algorithmic complexity.

Figure 8 System partitioning between FPGA and CPU domains. The FPGA handles all high-rate DSP (ADC interface, DDC, channelization, modulation/demodulation kernels, timing control) and interfaces to the CPU via DMA/FIFO over AXI4-Stream, PCIe, or Ethernet. The CPU runs flexible algorithms (FEC decoding, protocol stacks, applications) and provides control-plane functions (frequency tuning, AGC, calibration).

7.2 Processing Element Comparison

Platform	Sample Throughput	Latency	Power/GFLOP	Reconfigurability
FPGA	1–10 GSPS	10 ns – 10 μs	5–20 mW	Medium (recompile)
DSP (C66x, SHARC)	100–500 MSPS	1–100 μs	50–200 mW	High (firmware)
GPU	1–5 GSPS	100 μs – 10 ms	100–500 mW	High (CUDA/OpenCL)
CPU (ARM/x86)	10–100 MSPS	10 μs – 10 ms	500–2000 mW	Very high (software)

Table 20 SDR processing platform comparison (per GFLOP).

7.3 Typical Function-to-Platform Mapping

Function	Implementation	Rationale
ADC/DAC interface	FPGA	Wire-speed, deterministic timing
DDC/DUC	FPGA	Sample rate >>1 MSPS, parallel multiply
CIC decimation	FPGA	No multipliers needed, pure logic
Channelizer (PFB-FFT)	FPGA	Massive parallelism, deterministic
Modulation (simple)	FPGA	Low latency for TDMA timing
Demodulation (complex)	FPGA or DSP	Depends on modulation complexity
FEC encode/decode	DSP or CPU	Algorithmic complexity (Viterbi, LDPC)
Protocol stack (MAC)	CPU	State machine complexity, flexibility
Timing/scheduler	FPGA	Sub-microsecond determinism
Spectrum sensing	CPU	Complex analysis, display

Table 21 Function-to-platform mapping rationale.

7.4 Data Transport

The interface between FPGA and CPU must sustain the post-decimation data rate without dropping samples:

Interface	Bandwidth	Latency	Typical Use
AXI4-Stream (on-chip)	1–10 Gbps	<100 ns	SoC (Zynq, Intel SoC)
PCIe Gen3 x4	32 Gbps	1–5 μs	Discrete FPGA + host
10GbE	10 Gbps	10–50 μs	Networked SDR (HPSDR)
1GbE	1 Gbps	50–200 μs	Low-bandwidth SDR
USB 3.0	5 Gbps	0.1–1 ms	Consumer SDR dongles

Table 22 FPGA-to-CPU data transport options.

The ANAN-G2 (HPSDR architecture) uses Gigabit Ethernet, which provides 1 Gbps raw bandwidth — sufficient for multiple simultaneous DDC channels at 48–192 kSPS each, while also providing natural network isolation and long cable runs.

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8. Practical Considerations

8.1 DC Offset Correction

Direct-conversion and zero-IF receivers exhibit a DC offset from LO-to-RF leakage through the mixer. This produces a spectral spike at the center frequency that can mask weak signals.

Digital correction uses an IIR high-pass filter:

y[n] = x[n] - μ · avg[n] — Eq. (19)

avg[n] = (1 - α) · avg[n-1] + α · y[n] — Eq. (20)

Where μ ≈ 1.0, α = 2^-10 to 2^-16. The time constant must be slow enough not to distort low-frequency signal content. For SSB voice (300 Hz lower cutoff), α = 2^-14 at 48 kSPS gives a -3 dB point of approximately 3 Hz — well below the audio passband.

8.2 I/Q Imbalance Correction

Amplitude and phase mismatch between I and Q channels creates an unwanted image response — a mirror of the desired signal reflected about the tuned frequency. In analog I/Q systems (direct conversion), this is unavoidable due to component tolerances.

Parameter	Typical Uncorrected	After Digital Calibration
Amplitude imbalance	0.1–1.0 dB	<0.01 dB
Phase imbalance	1–5°	<0.1°
Image rejection	25–40 dB	>60 dB

Table 23 I/Q imbalance correction performance.

Adaptive correction using a 2×2 matrix:

I_corrected[n] = I’[n] — Eq. (21a)

Q_corrected[n] = α · Q’[n] + β · I’[n] — Eq. (21b)

Where α and β are adaptively estimated using LMS (Least Mean Square) or blind source separation algorithms. The adaptation minimizes the cross-correlation between corrected I and Q channels.

8.3 Spurious Management

Digital spurs arise from NCO phase truncation, finite-precision arithmetic, and clock feedthrough. Key mitigation strategies:

Spur Source	Mechanism	Mitigation	Typical Improvement
NCO phase truncation	Periodic error in sin/cos	Phase dithering	20–30 dB
NCO amplitude truncation	Quantized sine values	Taylor series correction	10–20 dB
ADC clock feedthrough	Digital switching on analog supply	Layout isolation, LDO filtering	10–30 dB
CIC passband aliasing	Folded out-of-band noise	Increased CIC order	6 dB per order
FIR coefficient quantization	Rounded filter coefficients	Wider coefficient word	6 dB per bit

Table 24 Digital spur sources and mitigations.

8.4 Phase Noise Budget

For coherent demodulation (PSK, QAM), the total phase noise from all sources must be below the modulation’s phase tolerance:

Source	Typical Contribution	Notes
LO synthesizer	-80 to -110 dBc/Hz @ 10 kHz	Dominates in superheterodyne
ADC clock jitter	-100 to -130 dBc/Hz @ 10 kHz	OCXO: <100 fs jitter
NCO (digital)	Negligible	Deterministic, no phase noise
PLL (carrier recovery)	Depends on loop BW	Integration of VCO noise

Table 25 Phase noise contributions by source.

For QPSK with a target BER of 10^-6, the integrated phase noise must be below approximately 5° RMS. For 16-QAM, this drops to approximately 2° RMS.

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9. Design Example: HF Direct-Sampling SDR Receiver

This section presents a complete worked design for an HF-band direct-sampling SDR receiver suitable for amateur radio and maritime communications (1.8–30 MHz).

9.1 System Requirements

Parameter	Requirement
Frequency range	1.8–30 MHz
Instantaneous bandwidth	62.5 MHz (full first Nyquist zone)
Channel bandwidth	100 Hz (CW) to 12 kHz (AM)
Minimum discernible signal	-130 dBm (500 Hz BW)
Blocking dynamic range	>120 dB
SFDR	>90 dB (in-channel)
Output data rate	48 kSPS complex I/Q per channel
Simultaneous channels	Up to 7

Table 26 HF SDR receiver system requirements.

9.2 Component Selection

Component	Selection	Key Specification
ADC	LTC2208 (Linear Tech)	16-bit, 130 MSPS, 79.2 dB SNR
Clock	OCXO, 125 MHz	Phase noise: -155 dBc/Hz @ 10 kHz, jitter <80 fs
LNA	Mini-Circuits PGA-103+	NF: 0.5 dB, OIP3: +37 dBm, G: 26 dB
Preselector	Switched BPF bank (160m–10m)	IL: <2 dB, rejection >60 dB
FPGA	Xilinx Artix-7 (XC7A100T)	101K LUTs, 4.9 Mb BRAM, 240 DSP48
CPU	ARM Cortex-A53 (CM5)	1.5 GHz quad-core, GbE
Interface	Gigabit Ethernet	1 Gbps, HPSDR protocol

Table 27 Component selection for HF SDR receiver.

9.3 Signal Budget

Point	Signal Level	Noise Floor	SNR
Antenna (30 MHz, 500 Hz BW)	-80 dBm	-147 dBm	67 dB
After preselector (IL=2 dB)	-82 dBm	-145 dBm	63 dB
After LNA (G=26 dB, NF=0.5 dB)	-56 dBm	-119.5 dBm	63.5 dB
ADC input	-56 dBm	-119.5 dBm	63.5 dB
ADC output (16-bit, 125 MSPS)	—	-174+10+81 = -83 dBFS	79 dB (ADC)
After DDC (500 Hz BW)	—	Processing gain: 44 dB	123 dB effective

Table 28 Signal level budget through the receiver chain.

9.4 FPGA Resource Utilization

Function	LUTs	DSP48 Slices	BRAM (Kb)
ADC interface (LVDS)	200	0	0
NCO (32-bit, quarter-wave LUT)	150	2	18
CIC filter (5th order, 128×)	1,200	0	0
Compensation FIR (21 taps)	400	11	2
Half-band filter (47 taps)	300	12	2
Channel FIR (63 taps)	500	16	4
Per DDC channel total	2,750	41	26
7 channels	19,250	287	182
GbE MAC + DMA	5,000	0	36
Timing/control	2,000	0	8
System total	26,250	287	226
Artix-7 100T capacity	101,440	240	4,860
Utilization	26%	120%	5%

Table 29 FPGA resource utilization estimate.

Note: DSP48 utilization exceeds 100%, indicating that either time-multiplexing of DSP slices is required (feasible since channel FIR runs at 488 kSPS, far below the DSP48’s 500 MHz clock), or the Artix-7 200T variant should be selected.

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10. References

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3. Tsui, J.B.Y., Digital Techniques for Wideband Receivers, 2nd ed., Artech House, 2001.
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12. Analog Devices, “Understanding High Speed ADC Testing and Evaluation,” Application Note AN-835, 2017.